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may 2015 docid027900 rev 1 1 / 15 this is information on a product in full production. www.st.com STL12N60M2 n - channel 600 v, 0. 400 typ., 6.5 a mdmesh? m2 power mosfet in a powerflat 5x6 hv package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STL12N60M2 600 v 0. 495 6.5 a 52 w ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? 100% avalanche tested ? zener - protected applications ? switching applications description this device is an n - channel power mosfet developed using mdmesh? m2 technolog y. thanks to its strip layout and an improved vertical structure, the device exhibits low on - resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. table 1: device summary order code marking package packing STL12N60M2 12n60m2 powerflat 5x6 hv tape and reel 1 2 3 4 powerfla t? 5x6 hv
contents STL12N60M2 2 / 15 docid027900 rev 1 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.1 electrical characteristics (curves) ...................................................... 6 3 test circuits ..................................................................................... 8 4 package information ....................................................................... 9 4.1 powerflat? 5x6 hv package information .................................... 10 4.2 powerflat? 5x6 packing information ........................................... 12 5 revision history ............................................................................ 14
STL12N60M2 electrical ratings docid027900 rev 1 3 / 15 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d (1) drain current (continuous) at t case = 25 c 6.5 a drain current (continuous) at t case = 100 c 4.1 i dm (2) drain current (pulsed) 26 a p tot total dissipation at t case = 25 c 52 w dv/dt (3) peak diode recovery voltage slope 15 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 t stg storage temperature - 55 to 150 c t j operating junction temperature notes: (1) limited by maximum junction temperature. (2) pulse width is limited by safe operating area. (3) i sd 6.5 a, di/d t=400 a/s; v ds (peak) < v (br)dss , v dd = 80% v (br)dss . (4) v ds 480 v. table 3: thermal data symbol parameter value unit r thj -case thermal resistance junction - case 2.4 c/w r thj -pcb (1) thermal resistance junction - pcb 50 notes: (1) when mounted on a 1 - inch2 fr - 4, 2 oz copper board. table 4: avalanche characteristics symbol parameter value unit i ar (1) avalanche current, repetitive or not repetitive 1.6 a e ar (2) single pulse avalanche energy 120 mj notes: (1) pulse width limited by t jmax . (2) starting t j = 25 c, i d = i ar , v dd = 50 v.
electrical characteristics STL12N60M2 4 / 15 doc id027900 rev 1 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 1 a v gs = 0 v, v ds = 600 v, t case = 125 c 100 i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 4.5 a 0.400 0.495 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 538 - pf c oss output capacitance - 29 - c rss reverse transfer capacitance - 1.1 - c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 106 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 7 - q g total gate charge v dd = 400 v, i d = 9 a, v gs = 10 v (see figure 15: "gate charge test circuit" ) - 16 - nc q gs gate - source charge - 2.3 - q gd gate - drain charge - 8.5 - notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . table 7: swi tching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 4.5 a r g = 4.7 , v gs = 10 v (see figure 14: "switching times test circuit for resistive load" and figure 19: "switching time waveform" ) - 9.2 - ns t r rise time - 9.2 - t d(off) turn - off delay t ime - 56 - t f fall time - 18 -
STL12N60M2 electrical characteristics docid027900 rev 1 5 / 15 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source- drain current - 9 a i sdm (1) source- drain current (pulsed) - 36 a v sd (2) forward on voltage v gs = 0 v, i sd = 9 a - 1.6 v t rr reverse recovery time i sd = 9 a, di/dt = 100 a/s, v dd = 60 v (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 284 ns q rr reverse recovery charge - 2.4 c i rrm reverse recovery current - 17 a t rr reverse recovery time i sd = 9 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 16: "test circuit for inductive load s witching and diode recovery times" ) - 404 ns q rr reverse recovery charge - 3.5 c i rrm reverse recovery current - 17.5 a notes: (1) pulse width is limited by safe operating area. (2) pulse test: pulse duration = 300 s, duty cycle 1.5%.
electrical characteristics STL12N60M2 6 / 15 doc id027900 rev 1 2.1 elect rical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STL12N60M2 electrical characteristics docid027900 rev 1 7 / 15 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : no rmalized v(br)dss vs temperature figure 12 : output capacitance stored energy figure 13 : source - drain diode forward characteristics t j (c) i d = 250 a v gs(th) 1.00 0.90 0.80 0.70 -50 0 (norm) 1.10 50 100 am03184v1
test circuits STL12N60M2 8 / 15 doc id027900 rev 1 3 test circuits figure 14 : switching times test circuit for resistive load figure 15 : gate charge test circuit figure 16 : test circuit for inductiv e load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform
STL12N60M2 package information docid027900 rev 1 9 / 15 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental complianc e. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information STL12N60M2 10 / 15 doc id027900 rev 1 4.1 powerflat? 5x6 hv package information fig ure 20 : powerflat? 5x6 hv package outline 8368143_rev_b bott om view side view se a ting plane top view pin #1 id b (x8) d2 e2 e a a1 a2 k l e d resin protrusion resin protrusion
STL12N60M2 package information docid027900 rev 1 11 / 15 table 9: powerflat? 5x6 hv mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 e 5.95 6.15 6.35 d2 4.30 4.40 4.50 e2 3.10 3.20 3.30 e 1.27 l 0.50 0.55 0.60 k 1.90 2.00 2.10 figure 21 : powerflat? 5x6 hv recommended footprint (dimensions are in mm) 3.04 4.31 0.77 0.5 5.4 1.9 0.73 3.77 6.4 8368143_rev_b_footprint
package information STL12N60M2 12 / 15 doc id027900 rev 1 4.2 powerflat? 5x6 packing information figure 22 : powerflat? 5x6 tape (dimensions are in mm) figure 23 : powerflat? 5x6 package orientation in carrier tape measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t re f .r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_ t ape_rev_c
STL12N60M2 package information docid027900 rev 1 13 / 15 figure 24 : powerflat? 5x6 reel
revision history STL12N60M2 14 / 15 doc id027900 rev 1 5 rev ision history table 10: document revision history date revision changes 22- may -2015 1 first release.
STL12N60M2 docid027900 rev 1 15 / 15 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time witho ut notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product . st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. info rmation in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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